AccelChip DSP Synthesis allows algorithm developers to take designs created in MATLAB and automatically synthesize a high-quality silicon implementation. A synthesis and verification environment, the product automatically converts MATLAB design from floating-point to fixed-point, then generates synthesizable VHDL or Verilog models, providing designers the ability to verify the algorithm and its implementation sooner.
Definitely a neat idea, if it works. When I see “automatically synthesize a high-quality silicon implementation” it brings out my inner skeptic. When going from a very high-level description to a low-level one, a synthesis tool needs to make intelligent guesses about the designer’s intentions. Does it optimize for speed or power consumption or die size? Does it try to balance the competing needs? The danger is that the compiler synthesizes a correct implementation that is perfectly useless because it fails to meet some other important criteria. Lisp solves this by allowing programmers to give the compiler hints about performance. I wonder if AccelChip DSP Synthesis has a similar facility.